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課程名稱 |
數位訊號處理架構設計
Digital Signal Processing in Vlsi Design |
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開課學期 |
112-1 |
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授課對象 |
電機資訊學院 電機工程學研究所 |
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授課教師 |
簡韶逸 |
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課號 |
EE5141 |
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課程識別碼 |
921 U9330 |
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班次 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期五2,3,4(9:10~12:10) |
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上課地點 |
博理112 |
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備註 |
總人數上限：80人 |
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課程簡介影片 |
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核心能力關聯 |
本課程尚未建立核心能力關連 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Part I: Basic Design Skills
Introduction to digital signal processing systems
Iteration bound
Pipeline and parallel processing
Retiming
Unfolding
Folding
Systolic array architecture
Scheduling and resource allocation
Processing element design
SoC and DSP architecture
Part II: Case Study
FFT
Motion estimator
Neural network |
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課程目標 |
1. 介紹數位訊號處理架構設計的基本技巧與常用模組
2. 本課程的重點是積體電路之硬體架構設計與低功耗電路設計 |
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課程要求 |
Homework: 40%
Midterm: 35%
Final project: 25% |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
K. K. Parhi, VLSI Digital Signal Processing Systems, John Wiley & Sons, 1999.
L. Wanhammar, DSP Integrated Circuits, Academic Process, 1999.
K. K. Parhi and T. Nishitani Ed., Digital Signal Processing for Multimedia Systems, Marcel Dekker, 1999.
B. Venkataramani and M. Bhaskar, Digital Signal Processors: Architecture, Programming and Applications, McGraw-Hill, 2002
P. Lapsley, J. Bier, A. Shoham, E. A. Lee, DSP Processor Fundamentals, IEEE Press, 1996.
L.-G. Chen, C.-T. Huang, C.-Y. Chen, and C.-C. Cheng, VLSI Design of Wavelet Transform, Imperial College Press, 2006.
D. Markovic and R. W. Brodersen, DSP Architecture Design Essentials, Springer, 2012.
A. C. C. Liu and O. M. K. Law, Deep Learning – Hardware Design, 2020.
Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel S. Emer, Efficient Processing of Deep Neural Networks, Morgan & Claypool Publishers, 2020. |
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評量方式
(僅供參考) |
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